This invention is directed to methods of making metal-oxide-semiconductor integrated circuits, and structures resulting therefrom, and more particularly to a method of making metal-oxide semiconductor integrated circuits where the sources and drains of the transistors are doped with a slow diffusing impurity, and the multilevel interconnect system insulating layer is arsenic-doped glass or a multilayer structure of phosphorus-doped or arsenic-doped glass upon undoped oxide.
In the fabrication of integrated circuits used primarily for logic applications it is desirable, and the trend has been, to reduce the size of the individual transistor, diode, resistor, etc elements to reduce chip size and/or put more elements on a single chip. At first photolithographic limitations were the sole limiting item in achieving greater packing density. However as photolithographic technology has improved, other factors such as lateral diffusion are becoming important in limiting minimum device sizes. Today transistor gates are 0.3 mils long and the lateral diffusion of sources and drains are 0.04 mils giving a channel length of 0.22 mils. Lateral diffusion now plays an important role in resisting efforts to further reduce device sizes. The present MOS circuits, particularly random access memories (RAMs) and microprocessors, are usually N-channel and fabricated with at least one level of polycrystalline silicon for gates and with phosphorus as the source and drain impurity. The multilevel interconnect system insulating layer is usually phosphorus glass. This fabrication process has problems however when trying to reduce the source and drain lateral diffusion. Phosphorus has a relatively large diffusion coefficient which causes further diffusion of the sources and drains during the high temperatures (typically 950-1000 degrees centigrade) required to cause the multilayer oxide to reflow. These process requirements limit the minimum diffusion depth (and consequently the minimum lateral diffusion) one can achieve.